１限 情報回路

今までせっせと書いたのに消えちゃった・・・
(# ゜Д゜) ムッキー

module Trans8(DI,STB,CLOCK,nCLEAR,RSTBD,SRDY,SB,STBD,RDY,SO);
	input [7:0] DI;
	input STB, CLOCK, nCLEAR ,RSTBD, SRDY;
	output [7:0] SB;
	output STBD, RDY,SO;
	reg [7:0] sb;
	reg [8:0] sr , sc;
	reg stbd, rdy, stb;
	reg set , shift;
	wire stsb;

	always@(posedge CLOCK or negedge nCLEAR)
		if(~nCLEAR) begin
			rdy <= 1;
			stbd <= 0;
			sb <= 0;
		end
		else begin
			stb <= STB;
			stbd <= RSTBD & (stbd | stsb);
			rdy <= ~stsb & SRDY;
			
			if(stsb) begin 
				sb[7:0] <= DI[7:0];
				set <= 1;
			end
			else if(set) begin
				sr <= {sb,1'b0};
				sc <= 0;
				set <= 0;
			end
			else begin
				sr <= {1'b1,sr[8:1]};
				sc <= {1'b1,sc[8:1]};
				shift <= &sc;
				if(shift) begin
					shift <= 0;
					rdy <= 1;
					stbd <= 1;
					sc <= 0;
					sb[7:0] <= DI[7:0];
					set <= 1;
				end
			end
		end
	assign SO = sr[0];	
	assign stsb = STB & ~stb;
	assign SB[7:0] = sb[7:0];
	assign STBD = stbd;
	assign RDY = rdy;
endmodule